Field-effect transistors (FETs) are commonly manufactured in a silicon layer and covered by stress liners that apply either tensile or compressive stress to the channels of the FETs. The purpose of these stress liners has been to improve the mobility in the channels. The type of stress that is applied depends upon the type of FET. Compressive stress is applied to the channel of a P-channel FET (PFET) and tensile stress is applied to the channel of an N-channel FET (NFET).
Such stressed FETs are also manufactured with thick sidewall spacers disposed on opposing sides of the channel. The sidewall spacers are used for aligning the source and drain at a distance from the opposing sides of the channel. This is done by implanting the source and drain from a direction normal to the surface of the silicon layer, using the sidewall spacers as masks.
Silicide regions are also located away from the channel so that reduce junction leakage and parasitic resistance are reduced. To make the manufacturing process more efficient and to position the silicide regions to laterally coincide with the source/drain locations, the same sidewall spacers are also used for locating the silicide regions.
After the sidewall spacers are built and used as masks, the stress liner is added over the entire FET structure including the sidewall spacers. As a result, the stress liner is spaced laterally away from the channel on each side by at least the distance of one of the sidewall spacers.